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| Rev 0; 2/06 XFP Laser Control and Digital Diagnostic IC General Description The DS1862 is a closed-loop laser-driver control IC with built-in digital diagnostics designed for XFP MSA. The laser control function incorporates average power control (APC) and allows extinction ratio control though a temperature indexed look-up table (LUT). The DS1862 monitors up to seven analog inputs, including temperature and monitor diode (MD) current, which are used to regulate the laser bias current and extinction ratio. Warning and alarm thresholds can be programmed to generate an interrupt if monitored signals exceed tolerance. Calibration is also provided internally using independent gain and offset scaling registers for each of the monitored analog signals. Settings such as programmed calibration data are stored in password-protected EEPROM memory. Programming is accomplished through an I2C*-compatible interface, which can also be used to access diagnostic functionality. Features Implements XFP MSA Requirements for Digital Diagnostics, Serial ID, and User Memory I2C-Compatible Serial Interface Automatic Power Control (APC) Extinction Ratio Control with Look-Up Table Seven Monitored Channels for Digital Diagnostics (Five Basic Plus Two Auxiliary) Internal Calibration of Monitored Channels (Temp, VCC2/3, Bias Current, Transmitted, and Received Power) Programmable Quick-Trip Logic for Turning Off Laser for Eye Safety Access to Monitoring and ID Information Programmable Alarm and Warning Thresholds Operates from 3.3V or 5V Supply 25-Pin CSBGA, 5mm x 5mm Package Internal or External Temperature Sensor -40C to +100C Operating Temperature Range One 8-Bit Buffered DAC DS1862 Applications Laser Control and Monitoring 10Gbps Optical Transceiver Modules (XFP) Laser Control and Monitoring Digital Diagnostics in Optical Transmission Pin Configuration TOP VIEW 1 A 2 3 4 5 Ordering Information PART DS1862B DS1862B+ TEMP RANGE -40C to +100C -40C to +100C PIN-PACKAGE 25 CSBGA (5mm x 5mm) 25 CSBGA (5mm x 5mm) +Denotes lead-free package. B C D E CSBGA (5mm x 5mm) Typical Operating Circuit appears at end of data sheet. *Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ______________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. XFP Laser Control and Digital Diagnostic IC DS1862 ABSOLUTE MAXIMUM RATINGS Voltage on Any Open-Drain Pin Relative to Ground.............................................-0.5V to +6.0V Voltage on MOD-DSEL, SDA, SCL, FETG, THRSET, TX-D, AUX1MON, AUX2MON, IBIASMON, RSSI, BIASSET, MODSET, EN1, and EN2 ............-0.5V to (VCC3 + 0.5V), not to exceed +6.0V Voltage on SC-RX-LOS, SC-RX-LOL, RX-LOS, SC-TX-LOS, MOD-NR, EN1, and EN2 ............-0.5V to (VCC2 + 0.5V), not to exceed +6.0V Operating Temperature Range .........................-40C to +100C EEPROM Programming Temperature Range .........0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See J-STD-020 Specification Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (VCC3 = +2.9V to +5.5V, TA = -40C to +100C, unless otherwise noted.) PARAMETER Main Supply Voltage Secondary Supply Voltage High-Level Input Voltage (SDA, SCL) Low-Level Input Voltage (SDA, SCL) High-Level Input Voltage (TX-D, MOD-DESEL, P-DOWN/RST) (Note 3) Low-Level Input Voltage (TX-D, MOD-DESEL, P-DOWN/RST) (Note 3) SYMBOL VCC3 VCC2 VIH VIL (Note 1) VCC2 not to exceed VCC3 (Note 2) IIH (max) = 10A IIL (max) = -10A CONDITIONS MIN +2.9 +1.6 0.7 x VCC3 GND 0.3 2 TYP MAX +5.5 +3.6 VCC3 + 0.5 0.3 x VCC3 VCC3 + 0.3 UNITS V V V V VIH IIH (max) = 10A V VIL IIL (max) = -10A -0.3 +0.8 V 2 _____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DC ELECTRICAL CHARACTERISTICS (VCC3 = +2.9V to +5.5V, VCC2 = +1.6V to +3.6V, TA = -40C to +100C, unless otherwise noted.) PARAMETER Supply Current High-Level Output Voltage (FETG) Low-Level Output Voltage (MOD-NR, INTERRUPT, SDA, and FETG) Resistor (Pullup) I/O Capacitance Leakage Current Leakage Current (SCL, SDA) Digital Power-On Reset Analog Power-On Reset SYMBOL ICC3 VOH CONDITIONS P-DOWN/RST = 1 IOH (max) = -2mA VCC3 0.5 0 9 (Note 4) -10 -10 1.0 2.0 12 0.4 15 10 +10 +10 2.2 2.6 MIN TYP 3 MAX 5 UNITS mA V DS1862 VOL RPU CI/O IL IL POD POA IOL (max) = 3mA V k pF A A V V DC ELECTRICAL CHARACTERISTICS--INTERFACE SIGNALS TO SIGNAL CONDITIONERS (VCC2 = +1.6V to +3.6V, VCC3 = +2.9V to +5.5V, TA = -40C to +100C, unless otherwise noted.) PARAMETER High-Level Input Voltage (SC-RX-LOS, SC-RX-LOL, and SC-TX-LOS) Low-Level Input Voltage (SC-RX-LOS, SC-RX-LOL, and SC-TX-LOS) SYMBOL VIH CONDITIONS IIH (max) = 100A MIN 0.7 x VCC2 TYP MAX VCC2 + 0.1 UNITS V VIL IIL (max) = -100A 0 VCC2 0.2 VCC2 0.4 VCC2 0.2 0.3 x VCC2 V VOH High-Level Output Voltage (EN1 and EN2) VOH2 VOH3 VOL VOL2 Leakage Current (SC-RX-LOS, SC-RX-LOL and SC-TX-LOS, RX-LOS) IOH (max) = -0.7mA VCC2 = 2.5V to 3.6V IOH (max) = -2mA VCC2 = 1.6V IOH (max) = -0.7mA IOL (max) = 0.7mA VCC2 = 2.5V to 3.6V IOL (max) = 2mA V 0.20 V 0.40 Low-Level Output Voltage (EN1, EN2, and RX-LOS) IL -10 +10 A _____________________________________________________________________ 3 XFP Laser Control and Digital Diagnostic IC DS1862 I2C AC ELECTRICAL CHARACTERISTICS (VCC3 = +2.9V to +5.5V, TA = -40C to +100C, unless otherwise noted.) PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus Free Time between STOP and START Conditions Start Hold Time Start Setup Time Data in Hold Time Data in Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL signals STOP Setup Time MOD-SEL Setup Time MOD-SEL Hold Time Aborted Sequence Bus Release Capacitive Load for Each Bus Line EEPROM Write Time SYMBOL fSCI tLOW tHIGH tBUF tHD:SDA tSU:SDA tHD:DAT tSU:DAT tR tF tSU:STO tHost_select_setup tHost_select_hold tMOD-DESEL_Abort CB tW (Note 5) 4-Byte write (Note 6) (Note 5) (Note 5) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 2 10 2 400 16 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns s ms s ms pF ms ANALOG OUTPUT CHARACTERISTICS (VCC3 = +2.9V to +5.5V, VCC2 = +1.6V to +3.6V, TA = -40C to +100C, unless otherwise noted.) PARAMETER IBIASSET IBIASSET (Off-State Current) IMODSET IMODSET (Off-State Current) Voltage on IBIASSET and IMODSET VTHRSET VTHRSET Drift VTHRSET Capacitance load APC Calibration Accuracy APC Temp Drift IBMD DNL IBMD INL IBMD Voltage Drift IBMD FS Accuracy SYMBOL IBIASSET IBIASSET IMODSET IMODSET VMAX VTHRSET CTHRSET +25C 0.200mA to 1.5mA 50A to 200A Sink, SRC_SNK_B = 0 Source, SRC_SNK_B = 1 Sink, SRC_SNK_B = 0 Source, SRC_SNK_B = 1 -5 -0.9 -0.9 -4.0 -4.0 Shutdown 0.01 Shutdown (Note 7) IMAX = 100A Across temperature (Note 8) 10 0.7 50 -5 CONDITIONS MIN 0.01 10 TYP MAX 1.50 100 1.20 100 3.0 1000 +5 1 25 +5 12 +0.9 +0.9 +4.0 +4.0 1.2 1.5 UNITS mA nA mA nA V mV % nF A % A LSB LSB %/V % 4 _____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC ANALOG OUTPUT CHARACTERISTICS (continued) (VCC3 = +2.9V to +5.5V, VCC2 = +1.6V to +3.6V, TA = -40C to +100C, unless otherwise noted.) PARAMETER IMODSET Accuracy SYMBOL CONDITIONS +25C IMODSET = 0.04mA to 1.2mA 75A range 150A range 300A range 600A range 1200A range 75A range 150A range 300A range 600A range 1200A range MIN -1.5 -0.9 -0.9 -0.9 -0.9 -0.9 -1.5 -1.5 -1.0 -1.0 -1.0 TYP MAX +1.5 +0.9 +0.9 +0.9 +0.9 +0.9 +1.5 +1.5 +1.0 +1.0 +1.0 5 1.2 1.5 30 UNITS % DS1862 IMODSET DNL LSB IMODSET INL LSB IMODSET Temp Drift IMODSET Voltage Drift IMODSET FS Accuracy APC Bandwidth IMD / IAPC = 1 (Note 4) 6 10 % %/V % kHz AC ELECTRICAL CHARACTERISICS--XFP CONTROLLER (VCC3 = +2.9V to +5.5V, VCC2 = +1.6V to +3.6V, TA = -40C to +100C, unless otherwise noted.) PARAMETER Time to Initialize TX-D Assert Time TX-D Deassert Time P-DOWN/RST Assert Time P-DOWN/RST Deassert Time MOD-DESEL Deassert Time INTERRUPT Assert Delay INTERRUPT Deassert Delay MOD-NR Assert Delay MOD-NR Deassert Delay RX-LOS Assert Time RX-LOS Deassert Time P-DOWN/RST Reset Time Shutdown Time SYMBOL tINIT tOFF tON tPDR-ON tPDR-OFF tMOD-DESEL tINT-ON tINT-OFF CONDITIONS VCC3 within 5% of nominal IBIAS and IMOD below 10% of nominal IBIAS and IMOD above 90% of nominal IBIAS and IMOD below 10% of nominal IBIAS and IMOD above 90% of nominal Time until proper response to I2C communication Time from fault to interrupt assertion Time from read (clear flags) to interrupt deassertion MIN 30 TYP MAX 200 5 1 100 200 2 100 500 0.5 0.5 100 100 10 30 UNITS ms s ms s ms ms ms s ms ms ns ns s s tMOD-NR-ON Time from fault to MOD-NR assertion Time from read (clear flags) to MOD-NR tMOD-NR-OFF deassertion tLOS-ON tLOS-OFF tRESET tFAULT Time from SC-RX-LOS assertion to RX-LOS assertion Time from SC-RX-LOS deassertion to RX-LOS deassertion Time from P-DOWN/RST assertion to initial reset Time from fault to IBIASSET, IMODSET, and IBMD below 10% _____________________________________________________________________ 5 XFP Laser Control and Digital Diagnostic IC DS1862 AC ELECTRICAL CHARACTERISICS--SOFT* CONTROL AND STATUS (VCC3 = +2.9V to +5.5V, VCC2 = +1.6V to +3.6V, TA = -40C to +100C, unless otherwise noted.) PARAMETER Soft TX-D Assert Time Soft TX-D Deassert Time Soft P-DOWN/RST Assert Time Soft P-DOWN/RST Deassert Time Soft MOD-NR Assert Delay Soft MOD-NR Deassert Delay Soft RX_LOS Assert Time Soft RX_LOS Deassert Time Analog Parameter data Ready (DATA-NR) SYMBOL tOFF_Soft tON_Soft tPDR-ON_Soft tMOD-NR-ON _Soft CONDITIONS IBIAS and IMOD below 10% of nominal IBIAS and IMOD above 90% of nominal IBIAS and IMOD below 10% of nominal MIN TYP MAX 50 50 50 200 50 50 50 50 500 UNITS ms ms ms ms ms ms ms ms ms tPDR-OFF_Soft IBIAS and IMOD above 90% of nominal Time from fault to MOD-NR assertion tMOD-NR-OFF Time from read (clear flags) to MOD-NR deassertion _Soft tLOS-ON_Soft tLOS-OFF_Soft Time from SC-RX-LOS assertion to RX-LOS assertion Time from SC-RX-LOS deassertion to RX-LOS deassertion *All SOFT timing specifications are measured from the falling edge of "STOP" signal during I2C communication. ANALOG INPUT CHARACTERISTICS (VCC3 = +2.9V to +5.5V, TA = -40C to +100C, unless otherwise noted.) PARAMETER IBMD Configurable Source or Sink (+/-) IBMD Voltage (IBMD - 0A) IBMD Input Resistance VBMD RBMD Source mode Sink mode IBMD range 0 to 1.5mA 400 SYMBOL CONDITIONS MIN 0.05 2.0 1.2 550 700 TYP MAX 1.50 UNITS mA V A/D INPUT VOLTAGE MONITORING (IBIASMON, AUX2MON, AUX1MON, RSSI, BMD) (VCC3 = +2.9V to +5.5V, TA = -40C to +100C, unless otherwise noted.) PARAMETER Input Resolution Supply Resolution Input/Supply Accuracy Update Rate Input/Supply Offset Full-Scale Input (IBIASMON and RSSI) Full-Scale Input (AUX1MON, AUX2MON, and VCC2/3) BMD (Monitor) (TX-P) SYMBOL VMON VCC2/3 ACC tFRAME1 tFRAME2 VOS At factory setting AUX1MON and AUX2MON disabled All channels enabled (Note 4) At factory setting At factory setting (Note 9) FS setting 2.4875 6.5208 CONDITIONS MIN TYP 610 1.6 0.25 48 64 0 2.5 6.5536 1.5 0.5 52 75 5 2.5125 6.5864 MAX UNITS V mV %FS ms LSB V V mA 6 _____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC FAST ALARMS AND VCC FAULT CHARACTERISTICS (VCC3 = +2.9V to +5.5V, VCC2 = +1.6V to +3.6V, TA = -40C to +100C, unless otherwise noted.) PARAMETER HIGHBIAS and TX-P Threshold FS VCC2/3 Fault Asserted Falling Edge Delay QT Temperature Coefficient QT Voltage Coefficient QT FS Trim Accuracy (4.2V, +25C) QT Accuracy (Trip) (INL) QT Voltco QT Tempco 1.5 2.480 -2 2.500 0 SYMBOL (Note 10) VCC2/3 (Note 11) -3 CONDITIONS MIN 2.48 TYP 2.5 MAX 2.52 75 +3 0.5 2.520 +2 0.5 3 UNITS mA ms % %/V mA LSB %/V % DS1862 NONVOLATILE MEMORY CHARACTERISTICS (VCC3 = +2.9V to +5.5V, unless otherwise noted.) PARAMETER Endurance (Write Cycle) Endurance (Write Cycle) SYMBOL +70C +25C CONDITIONS MIN 50k 200k TYP MAX UNITS Cycles Cycles All voltages are referenced to ground. Current into IC is positive, out of the IC is negative. Secondary power supply is used to support optional variable power-supply feature of the XFP module. If VCC2 is not used, (i.e., signal conditioners using 3.3V supply) VCC2 should be connected to the VCC3. Note 3: Input signals (i.e., TX-D, MOD-DESEL, and P-DOWN/RST have internal pullup resistors. Note 4: Guaranteed by design. Simulated over process and 50A < IBMD < 1500A. Note 5: CB--total capacitance of one bus line in picofarads. Note 6: EEPROM write begins after a stop condition occurs. Note 7: This is the maximum and minimum voltage on the MODSET and BIASSET pins required to meet accuracy and drift specifications. Note 8: For VTHRSET, offset may be as much as 10mV. Note 9: This is the uncalibrated offset provided by the factory; offset adjustment is available on this channel. Note 10: % FS refers to calibrated FS in case of internal calibration, and uncalibrated FS in the case of external calibration. Uncalibrated FS is set in the factory and specified in this data sheet FS (factory). Calibrated FS is set by the user, allowing a change in any monitored channel scale. Note 11: See the Monitor Channels section for more detail or VCC2 and VCC3 selection. Note 1: Note 2: _____________________________________________________________________ 7 XFP Laser Control and Digital Diagnostic IC DS1862 Timing Diagrams TX-D RESET-DONE VCC > VPOA P-DOWN/RST RESET-DONE INTERRUPT READ-FLAGS tPDR-OFF IBIASSET tINIT tINIT ON IMODSET tINIT OFF tINIT Figure 1. Power-On Initialization with P-DOWN/RST Asserted and TX-D/SOFT-TX-D Not Asserted VCC > VPOA TX-D P-DOWN/RST RESET-DONE INTERRUPT IBIASSET tINIT ON tINIT IMODSET tINIT OFF Figure 2. Power-On Initialization with P-DOWN/RST Not Asserted and TX-D/SOFT-TX-D Not Asserted (Normal Operation) 8 _____________________________________________________________________ READ-FLAGS READ-FLAGS XFP Laser Control and Digital Diagnostic IC DS1862 Timing Diagrams (continued) TX-F TX-D IBIASSET tOFF IMODSET tON Figure 3. TX-D Timing During Normal Operation OCCURRENCE OF FAULT FETG TX-D IBIASSET tFAULT IMODSET Figure 4. Detection of Safety Fault Condition _____________________________________________________________________ 9 XFP Laser Control and Digital Diagnostic IC DS1862 Timing Diagrams (continued) OCCURRENCE OF FAULT P-DOWN/RST tRESET FETG tINIT IBIASSET RESET-DONE IMODSET Figure 5. Successful Recovery from Transient Safety Fault Condition Using P-DOWN/RST tFAULT P-DOWN/RST tRESET RESET-DONE tFAULT OCCURRENCE OF FAULT FETG (FETG_POL = 1) IBIASSET IMODSET Figure 6. Unsuccessful Recovery from Transient Safety Fault Condition 10 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Timing Diagrams (continued) DS1862 OCCURRENCE OF MONITOR CHANNEL FAULT tINIT_ON INTERRUPT tINIT_OFF READ FLAGS Figure 7. Monitor Channel Fault Timing ____________________________________________________________________ 11 XFP Laser Control and Digital Diagnostic IC DS1862 Typical Operating Characteristics (TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE DS1862 toc01 SUPPLY CURRENT vs. TEMPERATURE DS1862 toc02 IBMD DRIFT vs. TEMPERATURE 0.5 0 IBMD DRIFT (%) -0.5 -1.0 -1.5 -2.0 SRC_SINK_B = 1 SRC_SINK_B = 0 DS1862 toc03 6.0 5.5 SUPPLY CURRENT (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 2.8 3.3 3.8 4.3 IBMD = 499.479A 4.8 5.3 SRC_SINK_B = 0 SRC_SINK_B = 1 6.0 5.5 SUPPLY CURRENT (mA) 5.0 4.5 4.0 SRC_SINK_B = 0 3.5 3.0 VCC3 = 5.5V, VCC2 = 1.6V -40 -15 10 35 IBMD = 499.479A 60 85 SRC_SINK_B = 1 1.0 -2.5 VCC3 = 5.5V, VCC2 = 1.6V -40 -15 10 35 IBMD = 499.479A 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C) TEMPERATURE (C) IBMD DRIFT vs. SUPPLY VOLTAGE DS1862 toc04 IMODSET DRIFT vs. TEMPERATURE DS1862 toc05 1.0 0.8 0.6 1.0 0.5 IMODSET DRIFT (%) 0 -0.5 -1.0 -1.5 INTEGRAL NONLINEARITY OF QUICK TRIPS 0.6 0.4 ERROR (LSB) 0.2 0 -0.2 -0.4 DS1862 toc06 0.8 IBMD DRIFT (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2.8 3.6 SRC_SINK_B = 0 SRC_SINK_B = 1 IBMD = 499.479A 4.4 5.2 -2.0 VCC3 = 5.5V, VCC2 = 1.6V -40 -15 10 35 IBMD = 499.479A 60 85 -0.6 -0.8 0 128 CODE (0-255) 256 SUPPLY VOLTAGE (V) TEMPERATURE (C) DIFFERENTIAL NONLINEARITY OF IMODSET DS1862 toc07 INTEGRAL NONLINEARITY OF IMODSET 0.15 0.10 ERROR (LSB) 0.05 0 -0.05 -0.10 -0.15 DS1862 toc08 0.20 0.15 0.10 ERROR (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 0 VCC3 = 4.2V, VCC2 = 1.6V 128 CODE (0-255) FSR = 75A 0.20 -0.20 0 VCC3 = 4.2V, VCC2 = 1.6V 128 CODE (0-255) FSR = 75A 256 256 12 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Pin Description NAME P-DOWN/RST SC-RX-LOS SC-RX-LOL THRSET VCC2 RX-LOS SCL FETG RSSI MODSET TX-D SDA EN1 EN2 BIASSET INTERRUPT MOD-NR AUX1MON AUX2MON BMD GND MOD-DESEL IBIASMON SC-TX-LOS VCC3 PIN A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 DESCRIPTION Power-Down/Reset Input. This multifunction pin is pulled high internally. See the Power-Down/Reset Pin section for additional information. Signal Conditioner Receiver Loss-of-Signal Input. This pin is an active-high input with LVCMOS/LVTTL voltage levels. Signal Conditioner Receiver Loss-of-Lock Input. This pin is an active-high input with LVCMOS/LVTTL voltage levels. Threshold Set Output. This pin is a programmable voltage source that can be used for Rx signal conditioner. 1.8V Power-Supply Input Receiver Loss-of-Signal. This open-drain output indicates when there is insufficient optical power. I2C Serial-Clock Input FET Gate Output. This pin can drive an external FET gate associated with safety fault disconnect. Received Power Signal Input Modulation Current Output. This pin is only capable of sinking current. Transmit Disable Input. This pin has an internal pullup resistor. I2C Serial-Data Input/Output Enable 1 Output. Functional control for signal conditioners. Enable 2 Output. Functional control for signal conditioners. Bias Current Output. This pin is only capable of sinking current. Interrupt. This open-drain output pin indicates a possible operational fault or critical status condition to the host. Indicating Module Operational Fault. Open-drain output. This pin indicates the status of the MOD-NR flag. Aux1 Monitor Input. This pin can be used to measure any voltage quantity. Aux2 Monitor Input. This pin can be used to measure any voltage quantity or external temperature sensor. Monitor Diode Current Input. This pin is capable of sourcing or sinking current. Ground Module Deselect Input. This pin must be pulled low to enable I2C communication. This pin is pulled high internally. Bias Monitor Input. This pin can be used to monitor the voltage across the laser. Signal Conditioner Transmitter Loss-of-Signal. This pin is an active-high input with LVCMOS/LVTTL voltage levels. 3.3V or 5V Power-Supply Input DS1862 ____________________________________________________________________ 13 XFP Laser Control and Digital Diagnostic IC DS1862 Block Diagram VCC2 VCC3 TEMPERATURE SENSOR COMPARATORS ALARM AND WARNING THRESHOLDS IBIASMON ADC 13 BIT MUX OFFSET GAIN AUX2MON RSSI AUX1MON BMD I TO V IBMD TX-P ALARM AND WARNING THRESHOLDS ALARM FLAGS MEASURED DATA WARNING FLAGS MASKING BITS RIGHT SHIFTING INT INTERRUPT WARNING FLAGS INTERRUPT ALARM FLAGS MASKING BITS MISC CONTROL SIGNALS VCC3 VCC3 VCC2 VCC2 ADDRESS R/W DATA BUS DS1862 LOWER MEMORY TABLE-SELECT BYTE TABLE 01h SERIAL ID DATA TABLE 02h EEPROM TABLE 03h LUT TABLE 04h MODULE CONFIG TABLE 05h THRSET VCC3 RPU MOD-DESEL SDA SCL I2C INTERFACE ADDRESS R/W DATA BUS BIAS AND MODULATION ENABLE TEMPERATURE CONTROLED WITH LUT BIASSET IBMD RX-LOS AEXT(IBMD) A HIGH-BIAS QT VCC3 THRSET MODSET INT SC-RX-LOS SC-RX-LOL SC-TX-LOS EN1 EN2 MOD-NR LOGIC HIGH-BIAS ALARM THRESHOLD IBIASSET TX-P HIGH TX_P ALARM THRESHOLD GND LOW TX_P ALARM THRESHOLD TX-P LOW TX_P ALARM HIGH TX_P ALARM TX-F VCC2 OR VCC3 SOFT TX-D HIGH-BIAS ALARM RPU RPU TX-D STARTUP INITIALIZATION AND LASER SAFETY SHUTDOWN BLOCK BIAS AND MOD ENABLE P-DOWN/RST FETG 14 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Detailed Description The DS1862's block diagram is described in detail within the following sections and memory map/memory description. On power-up, the BMD current ramps up to the previously saved current setting in EEPROM APC registers. While operating, the DS1862 monitors the BMD current. If it begins to deviate from the desired (set) IBMD value, then, again, the current on the BIASSET pin is adjusted to compensate. DS1862 Automatic Power Control (APC) The DS1862's APC is accomplished by closed-loop adjustment of the bias current (BIASSET) until the feedback current (BMD) from a photodiode matches the value determined by the APC registers. The relationship between the APC register and IBMD is given by: IBMD = 5.859A x APCC<7:0> + (1.464A x APCF<1:0>) where APCC<7:0> is the 8-bit value in Table 04h, byte 84h that controls the coarse BMD current and APCF<1:0> is the 2-bit value that controls the fine BMD current. The BMD pin appears as a voltage source in series with two resistors. The overall equivalent resistance of the BMD input pin can be closely approximated by the plot in Figure 8. The voltage that appears on the BMD pin, assuming no external current load, is 1.2V if BMD is in sink-current mode (SRC_SINK_B = 0) or 2.0V if BMD is set to source current (SRC_SINK_B = 1). This allows the photodiode to be referenced to either VCC3 or GND. When the control loop is at steady state, the BMD current setting matches the current that is measured by the IBMD voltage across the internal resistance. During a transient period, the DS1862 adjusts the current drive on the BIASSET pin to bring the loop into steady state. The DS1862 is designed to support loop gains of 1/20 to 10. Extinction Ratio Control Look-Up Table (LUT) The DS1862 uses a temperature indexed look-up table (LUT) to control the extinction ratio. The MODSET pin is capable of sinking current based on the 8-bit binary value that is controlling it. The DS1862 also features a user-configurable current range to increase extinction ratio resolution. Five current ranges, as described in Table 1, are available to control the current entering MODSET. Table 1. Selectable Current Ranges for MODSET LUT CURRENT RANGE TABLE 04h, BYTE 86h<2:0> 000 001 010 011 100 CURRENT RANGE (A) 0 to 75 0 to 150 0 to 300 0 to 600 0 to 1200 BMD RESISTANCE vs. BMD SUPPLY CURRENT 600 584 565 RBMD () 546 527 508 489 470 0 0 0.25 0.50 0.75 1.00 1.25 1.50 IBMD (mA) VBMD RBMD NOTE: VBMD IS CONTROLLED BY THE SRC_SINK BIT IN TABLE 04h BMD IBMD VOLTAGE Figure 8. Approximate Model of the BMD Input ____________________________________________________________________ 15 XFP Laser Control and Digital Diagnostic IC If the largest current range is selected, the maximum value of FFh (from LUT) corresponds to a 1200A sink current. Regardless of current range, the MODSET value always consists of 256 steps, including zero. IMODSET can be controlled automatically with the temperature-based look-up table, or by three other manual methods. Automatic temperature addressed look-up is accomplished by an internal or external temperature sensor controlling an address pointer. This pointer indexes through 127 previously loaded 8-bit current values stored in the LUT. Each one of the 127 temperature slot locations corresponds to a 2C increment over the -40C to +102C temperature range. Any temperature above or below these points causes the code in the first or last temperature slot to be indexed. Both the internal temperature sensor and an external sensor connected to AUX2MON are capable of providing a signal to control the extinction ratio automatically with an indexed LUT. Table 2 illustrates the relationship between the temperature and the memory locations in the LUT. DS1862 Automatic and manual control of MODSET is controlled by two bits: TEN and AEN that reside in Table 04h, Byte B2h. By default (from factory) TEN and AEN are both set, causing complete automatic temperature-based look-up. If TEN and/or AEN are altered, then the DS1862 is set to one of the manual modes. Table 3 describes manual mode functionality. Table 3. Truth Table for TEN and AEN Bits TEN AEN DS1862 LUT FUNCTIONALITY Manual mode that allows users to write a value directly to the LUT Value register (Table 04h, Byte B1h) to drive MODSET. While in this mode, the LUT index pointer register is not being updated, and no longer drives the LUT Value register. Manual mode that allows users to write a value directly to the LUT Value register (Table 04h, Byte B1h) to drive MODSET. While in this mode, the LUT index pointer register is still being updated, however it no longer drives the LUT Value register. Manual mode that allows users to write a value to the LUT index pointer (Table 04h, Byte B0), then the DS1862 updates the LUT Value register (Table 04h, Byte B1h) based on the user's index pointer. Automatic mode (factory default). This mode automatically indexes the LUT based on temperature, placing the resulting LUT address in the LUT index pointer register (Table 04h, Byte B0h). Then the MODSET setting is transferred from that LUT address to the LUT Value register (Table 04h, Byte B1h). Lastly the IMODSET is set to the new MODSET code. 0 0 0 1 Table 2. Temperature Look-Up Table TEMPERATURE (C) < -40 -40 -38 -36 -- +96 +98 +100 +102 > +102 CORRESPONDING LOOK-UP TABLE ADDRESS 80h 80h 81h 82h -- C4h C5h C6h C7h C7h 1 1 1 0 16 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Monitor Channels The DS1862 has seven monitored voltage signals that are polled in a round-robin multiplexed sequence and are updated with the frame rate, tFRAME. All channels are read as 16-bit values, but have 13-bit resolution, and with the exception of temperature measurements, all channels are stored as unsigned values. The resulting 16-bit value for all monitored channels, except internal temperature, is calculated by internally averaging the analog-to-digital result 8 times. The resulting internal temperature monitor channel is averaged 16 times. See the Internal Calibration section for a complete description of each channel's method(s) of internal calibration. The AUX1MON, AUX2MON, and VCC2/3 monitor channels are optional and can be disabled. This feature allows for shorter frame rate for the essential monitor channels. Channels that can not be disabled are: internal temperature, BMD, RSSI, and IBIASMON. A table of full-scale (FS) signal values (using factory internal calibration without right shifting) and the resulting FS code values for all seven channels is provided below. Measuring Temperature--Internal or External The DS1862 is capable of measuring temperature on three different monitor channels: internal temperature sensor, AUX1MON, and AUX2MON. Only the internal temperature and AUX2MON channels are capable of indexing the LUT to control the extinction ratio. To use an external temperature sensor on AUX2MON, the TEMP_INT/EXT bit in Table 04h, Byte 8Bh, must be set. While AUX2MON controls the extinction ratio, the internal temperature sensor does not stop running; despite extinction ratio control by AUX2MON, it is this internal temperature signal that continues to control the status of temperature flags. Also when TEMP_INT/EXT = 1, the internal temperature clamps at -40C and +103.9375C, and when TEMP_INT/EXT = 0 it clamps at -120C and +127.984C. AUX2MON, however, does have its own flag to indicate an out-of-tolerance condition and assert the INTERRUPT pin. Both AUX1MON and AUX2MON can be used to measure temperature as a function of voltage on their respective pins. They can be enabled by selecting either 0h or 4h from Table 5. Internal (or external) calibration may be required to transmute the input voltage to the desired two's-complement digital code, readable from the result registers in lower memory, Bytes 6Ah, 6Bh and 6Ch, 6Dh. Measuring VCC2/3 The DS1862 has the flexibility to internally measure either VCC2 or VCC3 to monitor supply voltage. VCC2 or VCC3 is user selectable by the VCC2/3_Sel bit in Table 01h, Byte DCh. To remove VCC2/3 from the round-robin monitor update scheme, despite having VCC2 or VCC3 selected to be monitored, the Reserve_EN bit in Table 04h, Byte 8Bh can be programmed to a 0. The analog power-on-reset flag, POA, indicates the status of VCC3 power supply. Even though POA seems to behave similarly to VCC2/3 monitor channel, it is completely separate and has no connection. RESERVE_EN 0 0 1 1 VCC2/3_Sel 0 1 0 1 RESULT VCC2/3 result not enabled. VCC2/3 result not enabled. VCC3 is being measured. VCC2 is being measured. DS1862 Measuring APC and Laser Parameters--BMD, IBIASMON, RSSI BMD and BIASSET are used to control and monitor the laser functionality. Regardless of the set BMD current in the APC register, the DS1862 measures BMD pin current and uses this value not only to adjust the current on the BIASSET pin, but also to monitor TX-P as well. The IBIASMON pin is used to input a voltage signal to the DS1862 that can be used to monitor the bias current through the laser. This monitor channel does not drive the HIGHBIAS quick-trip (QT) alarms for safety Table 4. Monitor Channel FS and LSB Detail SIGNAL Temperature VCC2/3 IBIASMON RSSI AUX1MON AUX2MON BMD (TX-P) +FS SIGNAL 127.984C 6.5528V 2.4997V 2.4997V 6.5528V 6.5528V 1.5mA +FS (hex) 7FF8 FFF8 FFF8 FFF8 FFF8 FFF8 FFF8 -FS SIGNAL -120C 0V 0V 0V 0V 0V 0mA -FS (hex) 8800 0000 0000 0000 0000 0000 0000 LSB 0.0625C 100V 38.147V 38.147V 38.147V 38.147V 22.888nA ____________________________________________________________________ 17 XFP Laser Control and Digital Diagnostic IC DS1862 fault functionality, current on the BIASSET pin is monitored by the DS1862 to control the HIGHBIAS quick trip. Similar to TX-P, the RSSI pin is used to measure the received power, RX-P. Measuring Voltage Quantities using AUX1MON and AUX2MON AUX1MON and AUX2MON are auxiliary monitor inputs that may be used to measure additional parameters. AUX1/2MON feature a user-selectable register that determines the measured value's units (i.e., voltage, current, or temperature). In addition to indicating units, some of the 4-bit op-codes, in Table 5, also place the part in special modes used for alarms and faults internally. Whichever units' scale is selected, the DS1862 is only capable of measuring a positive voltage quantity, therefore internal or external calibration may be required to get the binary value to match the measured quantity. A table of acceptable units and/or their corresponding user-programmable 4-bit op-code is provided below. Alarms and Warning Flags Based on Monitor Channels All of the monitor channels feature alarm and warning flags that are asserted automatically as user-programmed thresholds are internally compared with monitor channel results. Flags may be set, which, if not masked, will generate an interrupt on the INTERRUPT pin or generate a safety fault. Whenever V CC2/3 , AUX2MON, AUX1MON, RSSI, and internal temperature go beyond their threshold trip points and the corresponding mask bit is 0, an interrupt is generated on the INTERRUPT pin and a corresponding warning or alarm flag is set. Similarly, a safety fault occurs whenever BMD or BIASSET go beyond threshold trip points. When this happens, the FETG pin immediately asserts and BIASSET and MODSET currents are shut down. Table 5. AUX1/2MON Functionality Selection (Unit Selection) VALUE 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1101b 1110b 1111b DESCRIPTION OF AUX1/2MON INTENDED USE (UNITS OF MEASURE) Auxiliary monitoring not implemented APD bias voltage (16-bit value is voltage in units of 10mV) Reserved TEC current (mA), (16-bit value is current in units of 0.1mA) Laser temperature (same encoding as module temperature) Laser wavelength +5V supply voltage (encoded as primary voltage monitor) +3.3V supply voltage (encoded as primary voltage monitor) +1.8V supply voltage (encoded as primary voltage monitor) (VCC2) -5.2V supply voltage (encoded as primary voltage monitor) +5V supply current (16-bit value is current in 0.1mA) +3.3V supply current (16-bit value is current in 0.1mA) +1.8V supply current (16-bit value is current in 0.1mA) -5.2V supply current (16-bit value is current in 0.1mA) Monitor Channel Conversion Example Table 6 provides an example of how a 16-bit ADC code corresponds to a real life measured voltage using the factory-set calibration on either RSSI or IBIASMON. By factory default, the LSB is set to 38.147V. Table 6. A/D Conversion Example MSB (BIN) 11000000 10000000 LSB (BIN) 00000000 10000000 VOLTAGE (V) 1.875 1.255 To calculate VCC2, VCC3, AUX1MON, or AUX2MON, convert the unsigned 16-bit value to decimal and multiply by 100V. To calculate the temperature (internal), treat the two'scomplement value binary number as an unsigned binary number, then convert it to decimal and divide by 256. If the result is grater than or equal to 128, subtract 256 from the result. Temperature: high byte = -128C to +127C signed; low byte = 1/256C. Table 7. Temperature Bit Weights S 2-1 26 2-2 25 2-3 24 2-4 23 2-5 22 -- 21 -- 20 -- 18 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Table 8. Temperature Conversion Examples MSB (BIN) 01000000 01000000 01011111 11110110 11011000 LSB (BIN) 00000000 00001000 00000000 00000000 00000000 TEMPERATURE (C) +64 +64.03215 +95 -10 -40 loaded into the appropriate channels' Gain register. This requires forcing two known voltages on to the monitor input pin. For best results, one of the forced voltages should be the NULL input and the other should be 90% of FS. Since the LSB of the least significant bit in the digital reading register is known, the expected digital results are also known for both the null and FS value inputs. Figure 9 describes the hysteresis built into the DS1862's LUT functionality. DS1862 Internal Calibration The DS1862 has two means for scaling an analog input to a digital result. The two devices alter the gain and offset of the signal to be calibrated. All of the inputs except internal temperature have unique registers for both the gain and the offset that can be found in Table 04h. See the table below for a complete description of internal calibration capabilities including right-shifting for all monitor channels. M6 M5 DECREASING TEMPERATURE MEMORY LOCATION M4 M3 Table 9. Internal Calibration Capabilities SIGNAL Temperature VCC2/3 IBIASMON RSSI (RX-P) AUX1MON AUX2MON BMD (TX-P) INTERNAL SCALING -- x x x x x x INTERNAL OFFSET x x x x x x x RIGHTSHIFTING -- -- x x x x x M2 INCREASING TEMPERATURE M1 2 4 6 8 TEMPERATURE (C) 10 12 Figure 9. Look-Up Table Hysteresis To scale a specific input's gain and offset, the relationship between the analog input and the expected digital result must be known. The input that would produce a corresponding digital result of all zeroes is the null value (normally this input is GND). The input that would produce a corresponding digital result of all ones is the full-scale (FS) value minus one LSB. The FS value is also found by multiplying an all ones digital value by the weighted LSB. For example, a digital reading is 16 bits long, assume that the LSB is known to be 50V, then the FS value would be 216 x 50V = 3.2768V. A binary search can be used to find the appropriate gain value to achieve the desired FS of the converter. Once the gain value is determined, then it can be With the exception of BMD, which can source or sink current, all monitored channels are high impedance and are only capable of directly measuring a voltage. If other measured quantities are desired, such as: light, frequency, power, current etc., they must be converted to a voltage. In this situation the user is not interested in voltage measurement on the monitored channel, but the measurement of the desired parameter. Only the relationship between the indirect measured quantity (light, frequency, power, current, etc.) to the expected digital result must be known. An example of gain scaling using the recommended binary search procedure is provided with the following pseudo-code. To help will the computation, two integers need to be defined: count 1 and count 2. CNT1 = NULL / LSB and CNT2 = 90%FS / LSB. CLAMP is the largest result that can be accommodated. ____________________________________________________________________ 19 XFP Laser Control and Digital Diagnostic IC DS1862 /* Assume that the Null input is 0.5V. */ /* In addition, the requirement for LSB is 50V. */ FS = 65536 * 50e-6; /* 3.2768 */ CNT1 = 0.5 / 50e-6; /* 10000 */ CNT2 = 0.90*FS / 50e-6; /* 58982 */ /* Thus the NULL input of 0.5V and the 90% of FS input is 2.94912V. */ set the trim-offset-register to zero; set Right-Shift register to zero (Typically zero. See the Right-Shifting section); gain_result = 0h; CLAMP = FFF8h/2^(Right_Shift_Register); For n = 15 down to 0 begin gain_result = gain_result + 2^n; Force the 90% FS input (2.94912V); Meas2 = read the digital result from the part; If Meas2 >= CLAMP then gain_result = gain_result - 2^n; Else Force the NULL input (0.5V); Meas1 = read the digital result from the part; if (Meas2 - Meas1) > (CNT2 - CNT1) then gain_result = gain_result - 2^n; end; Set the gain register to gain_result; The gain register is now set and the resolution of the conversion will best match the expected LSB. The next step is to calibrate the offset of the DS1862. With the correct gain value written to the gain register, again force the NULL input to the monitor pin. Read the digital result from the part (Meas1). The offset value is equal to negative value of Meas1. (-1)MEAS1 OFFSET _ REGISTER = 4 The calculated offset is now written to the DS1862 and the gain-and offset-scaling procedure is complete. Right-Shifting A/D Conversion Result (Scalable Dynamic Ranging) Right-shifting is a digital method used to regain some of the lost ADC range of a calibrated system. If rightshifting is enabled, by simply loading a non-zero value into the appropriate Right-Shifting Register, then the DS1862 shifts the calibrated result just before it is stored into the monitor channels' register. If a system is calibrated so the maximum expected input results in a digital output value of less than 7FFFh (50% of FS), then it is a candidate for using the right-shifting method. If the maximum desired digital output is less than 7FFFh, then the calibrated system is using less than 1/2 the ADC's range. Similarly, if the maximum desired digital output is less than 1FFFh, then the calibrated system is only using 1/8th the ADC's range. For example, if an applied maximum analog signal yields a maximum digital output less than 1FFCh, then only 1/8th of the ADC's range is used. Right-shifting improves the resolution of the measured signal as part of internal calibration. Without right-shifting, the 3 MS bits of the ADC will never be used. In this example, a value of 3 for the right-shifting maximizes the ADC range and a larger gain setting must be loaded to achieve optimal conversion. No resolution is lost since this is a 13-bit converter that is left justified. The value can be right-shifted 3 times without losing any resolution. The following table describes when the right-shifting method can be effectively used. Table 10. Right-Shifting Selection OUTPUT RANGE USED WITH ZERO RIGHT-SHIFTS 0h .. FFFFh 0h .. 7FFFh 0h .. 3FFFh 0h .. 1FFFh 0h .. 0FFFh NUMBER OF RIGHTSHIFTS NEEDED 0 1 2 3 4 20 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Warning and Alarm Logic Based on AUX1/2MON, VCC2/3, Temp, RX-P, and IBIASMON The DS1862 is capable of generating an alarm and/or warning whenever an analog monitored channel goes out of a user-defined tolerance. Temperature, bias current (based on IBIASMON), receive power (based on RSSI), AUX1MON, AUX2MON, and VCC2/3, are monitored channels that generate latched flags. See the figure below for more detail pertaining to AUX1MON and AUX2MON. Flags are latched into a high state the first time a monitored channel goes out of the defined operating window and for each monitored signal there is a Mask bit that can be set to prevent the corresponding alarm or warning flag from being set. Once a flag is set, it is cleared by simply reading its memory location. DS1862 AUX1/2MON LOGIC AUX1MON (PIN) ADC 4-BIT UNIT SELECT C THRESHOLD AUX1MON *COMPARATOR LOGIC IS DUPLICATED FOR HIGH AND LOW ALARMS AND WARNINGS. AUX2MON (PIN) ADC C THRESHOLD AUX2MON MASK BIT AUX1MON (APD MODE) AUX2MON (APD MODE) AUX1MON (LASER WL MODE) AUX2MON (LASER WL MODE) AUX1MON (VEE5 MODE) AUX2MON (VEE5 MODE) AUX1MON (VCC2 MODE) AUX2MON (VCC2 MODE) AUX1MON (TEC MODE) AUX2MON (TEC MODE) AUX1MON (VCC5 MODE) AUX2MON (VCC5 MODE) AUX1MON (VCC3 MODE) AUX2MON (VCC3 MODE) LATCH LATCHED-APDSUPPLY-FAULT LATCH LATCHED-TECFAULT LATCH LATCHEDWAVELENGH-UL LATCH LATCHED-VCC5 LATCH LATCH LATCHED-VEE5 LATCHED-VCC3 LATCH LATCHED-VCC2 ANY FLAG INTERRUPT (PIN) CORRESPONDING MASK BIT Figure 10. AUX1/2 Monitor Logic ____________________________________________________________________ 21 XFP Laser Control and Digital Diagnostic IC DS1862 Warning and Alarm Logic Based on Signal Conditioners The DS1862 also has flags that are set by certain logical conditions on signal conditioner (SC) pins: SC-RX-LOL, SC-RX-LOS, SC-TX-LOS. Similarly, for each latched signal conditioner flag there are also mask bits that are capable of preventing the alarm or warning flag from causing an INTERRUPT pin to assert. Again, flags are cleared automatically whenever their memory address is read. See Figure 11 for more detail. as fast alarms) that is capable of shutting down the LASER with the FETG pin in conjunction with shutting down IMODSET and IBIASSET. IBMD and IBIASSET currents are measured and are compared with userdefined trip points to set the quick-trip flags: QT LOW TX-P, QT HIGH TX-P, and QT HIGH BIAS. These flags are also capable of being masked to prevent FETG from being asserted when an out-of-tolerance condition is detected. FETG is not asserted by setting the TX-D pin, SOFT TX-D, or P-DOWN/RST pin to a high state, however, IMODSET, and IBIASSET will shut down. See Figure 12 for more detail. Quick-Trip Logic and FTEG Shutdown Functionality In addition to alarms and warnings, the DS1862 also has quick-trip (QT) functionality (sometimes referred to SIGNAL CONDITIONER AND MISCELLANEOUS LOGIC SC-TX-LOS (PIN) LATCHED-TX-FAULT LATCHED-TX-FAULT HIGH TX-P LOW TX-P HIGH BIAS LATCH LATCH LATCHED-TX-NR LATCH LATCHED-RX-NR SC-RX-LOL (PIN) P-DOWN/RST (PIN) LATCH SC-RX-LOS (PIN) TIMER LATCHED-RESET-DONE LATCH SC-RX-LOS (PIN) LATCHEDRX-LOS LATCH RX-LOS (PIN) *OPEN DRAIN SC-RX-LOL (PIN) LATCHED RX-CDR-NL LATCH SC-RX-LOL (PIN) TX-FAULT VCC2-FAULT MOD-NR (PIN) *OPEN DRAIN ANY FLAG ANY MASK BIT LATCHEDMOD-NR INTERRUPT (PIN) Figure 11. Signal Conditioner and Other Logic 22 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DS1862 SHUTDOWN LOGIC LATCH LATCHED-TX-FAULT BMD (PIN) (TX-P CURRENT) ADC THRESHOLD LOW TX-P MASK QT LOW TX-P FLAG BMD (PIN) (TX-P CURRENT) ADC THRESHOLD HIGH TX-P MASK QT HIGH TX-P FLAG FETG_POL FETG (PIN) BIASSET (PIN) (BIASSET CURRENT) ADC THRESHOLD BIAS HIGH MASK QT BIAS HIGH FLAG 0 1 FETG_POL DRIVE A P-CHANNEL SWITCH DRIVE A N-CHANNEL SWITCH SOFT TX-D P-DOWN/RST (PIN) TX-D (PIN) SAFETY FLAG SOFT P-DOWN/RST SHUTDOWN FLAG QT LOW TX-P FLAG QT HIGH TX-P FLAG QT BIAS HIGH FLAG LATCH SAFETY FLAG Figure 12. Safety Fault and Shutdown Logic The polarity of the FETG pin can also be reversed by setting the FETG_POL bit. Once a safety fault has occurred, the FETG pin and all of the attendant flags can only be reset by pulsing the P-DOWN/RST pin high for the reset time, tRESET, or by toggling the P-DOWN/RST bit in Byte 6Eh, bit 4. See the Power-Down/Reset Pin section for more details. after the safety condition has been rectified. See the timing diagrams for proper pin timing. Power-Down Functionality During power-down mode IBIASSET and IMODSET drop below 10A, effectively shutting down the laser. FETG is not asserted and safety faults do not occur during this period. During power-down, I2C communication is still active, but the signal conditioner pins EN1 and EN2 are noncontrollable and automatically change to the states: EN1 = 1 and EN2 = 0. Other internal flags/signals that are based on the signal conditioner inputs still reflect the status on the signal conditioner pins during power-down. For example, RX-LOS still reflects the status of SC-RX-LOS, and MOD-NR still reflects the logical states for the signal conditioner pins. Similarly, it is possible for FETG to be asserted, even though the BIASSET and MODSET currents are shut down. However, during power-down and a short period, tPDR-OFF, during powerup, TX-P Low flag is ignored (internally automatically masked out) and does not contribute to FETG's logic. Power-Down/Reset Pin The P-DOWN/RST pin is a multifunction input pin that resets and/or powers down the DS1862. Since the pin is internally pulled up, its normal state is released, which corresponds to power-down mode. If the P-DOWN/RST pin is released, or driven high, the DS1862 responds by shutting down the MODSET and BIASSET currents. Once the pin is pulled low, operation continues (if not inhibited by a safety fault). Besides powering down the DS1862, a high-going pulse with minimum reset time, tRESET, can be applied to the P-DOWN/RST pin. This is necessary to restart the DS1862, especially if it is in a safety shutdown condition and needs to be restarted ____________________________________________________________________ 23 XFP Laser Control and Digital Diagnostic IC DS1862 During an asserted period of P-DOWN/RST (DS1862 in power-down), and VCC3 is cycled, the DS1862 remains in power-down mode upon power-up. While in powerdown mode the INTERRUPT pin does not assert. Once VCC3 has returned, the reset done flag asserts after the interrupt assert delay, tINIT ON. Reset Functionality Besides powering down the DS1862, the P-DOWN/RST pin also functions to reset the DS1862. After a highgoing pulse of time tRESET, several events occur within the DS1862. First, MODSET and BIASSET currents shut down and are then reinstated. Second, between the rising edge of the reset pulse and the assertion of the reset-done flag (tINIT), the low TX-P flag is ignored and does not cause FETG to trip. After time tINIT, the low TX-P flag becomes functional. Also, at this time, the reset-done flag is asserted, causing an interrupt to be generated. If there are no faults before tINIT, then no interrupts are asserted on the INTERRUPT pin. If VCC3 is powered up while P-DOWN/RST is high, then the reset-done flag must be cleared twice. The first time the reset-done flag is generated by VCC3 powering up, the second time reset-done is generated by a falling edge on P-DOWN/RST. If VCC3 is continuously powered while P-DOWN/RST is low then only one resetdone flag needs to be cleared. See the timing diagrams for graphical detail. EEPROM as well as several control bytes for various functions. Table 02h is strictly user EEPROM that is protected by a host password. Table 03h is strictly used for controlling the extinction ratio with an LUT. Table 04h is a multifunction space that contains internal calibration values for monitored channels, LUT index pointers, and miscellaneous control bytes. Table 05h is factory programmed and stores SCALE values for use with suggested external temperature sensors. Also, one byte in Table 05h controls the THRSET voltage source and is completely accessible without any password protection. See the Memory section for a more complete detail of each byte's function, as well as Table 11 for read/write permissions for each Byte. Many nonvolatile memory locations (listed within the Detailed Register Description section) are actually SRAMShadowed EEPROM, which are controlled by the SEEB bit in Table 4, Byte B2h. The DS1862 incorporates SRAM-shadowed EEPROM memory locations for key memory addresses that may be rewritten many times. By default the Shadowed EEPROM Bit, SEEB, is not set and these locations act as ordinary EEPROM. By setting SEEB, these locations begin to function like SRAM cells, which allow an infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, t WR . Because changes made with SEEB enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-up value is the last value written with SEEB disabled. This function can be used to limit the number of EEPROM writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times EEPROM is written. The Memory Map description indicates which locations are shadowed-EEPROM. DS1862 Memory Map Memory Organization The DS1862 features six separate memory tables that are internally organized into four byte rows. The Lower Memory is addressed from 00h to 7Fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PE), and the Table Select byte. Table 01h primarily contains user 24 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DS1862 DEC hex 0 0 I2C SLAVE ADDRESS A0h 00h LOWER MEMORY DIGITAL DIAGNOSTIC FUNCTIONS PASSWORD ENTRY (PWE) (4 BYTES) 127 7F TABLE SELECT BYTE 7Fh 128 80 80h TABLE 01h TABLE 00h XFP MSA SERIAL ID DATA 80h TABLE 02h 80h TABLE 03h 80h TABLE 04h CONTROL AND CONFIGURATION TABLE (72 BYTES) BBh C7h 80h TABLE 05h OPTIONAL SCALE VALUES AND THRSET CONTROL 87h USER EEPROM DATA MODULATION DAC LUT 220 DC MISC CONTROL BITS 255 FF FFh FFh Figure 13. General View of DS1862 Memory Organization Register Map Table 11. Permission Table PERMISSION <0> <1> <2> <3> <4> <5> <6> <7> READ WRITE At least one byte in this row is different than the rest of the bytes, so look at each byte separately for permissions. ALL ALL ALL MODULE ALL NEVER NEVER ALL MODULE HOST MODULE FACTORY HOST MODULE ____________________________________________________________________ 25 XFP Laser Control and Digital Diagnostic IC DS1862 LOWER MEMORY (00H-7FH) ADDRESS (hex) 00<0,2> 08<2> 10<2> 18<2> 20<2> 28<2> 30<2> 38<0,2> 40<1> 48<1> 50<1> 58<1> 60<1> 68<1> 70<0,1> 78<0,1> BYTE (hex) 01 50 51 52 53 54 55 56 WORD 0 BYTE 0/8 EE BYTE 1/9 WORD 1 BYTE 2/A BYTE 3/B WORD 2 BYTE 4/C BYTE 5/D WORD 3 BYTE 6/E BYTE 7/F Signal Cond Temp Warn Lo VCC3 Warn Lo* Bias Warn Lo TX-P Warn Lo RX-P Warn Lo Aux1 Warn Lo Aux2 Warn Lo Temp Alarm Hi VCC3 Alarm Hi* Bias Alarm Hi TX-P Alarm Hi RX-P Alarm Hi Aux1 Alarm Hi Aux2 Alarm Hi EE Reserved SRAM EE Reserved SRAM Temp Alarm Lo VCC3 Alarm Lo* Bias Alarm Lo TX-P Alarm Lo RX-P Alarm Lo Aux1 Alarm Lo Aux2 Alarm Lo Reserved Reserved SRAM Tx/Rx Misc Flags Rx/Rx Misc Mask Reserved Reserved SRAM Temp Warn Hi VCC3 Warn Hi* Bias Warn Hi TX-P Warn Hi RX-P Warn Hi Aux1 Warn Hi Aux2 Warn Hi Reserved SRAM SRAM Reserved SRAM SRAM VCC5/3/2 Vee Warn Flags VCC5/3/2/Vee Warn Mask Reserved SRAM Reserved SRAM Temp/Res/Bias/ RxP/Aux1/Aux2/ TxP Alarm Res Alarm Temp/Res/Bias/ RxP/Aux1/Aux2/ TxP Mask Res Mask Temp Value RX-P Value Reserved Host PW BYTE/WORD NAME Signal Cond<1> <1> Temp/Res/Bias/ RxP/Aux1/Aux2/ TxP Warn Res Warn Temp/Res/Bias/ RxP/Aux1/Aux2/ TxP Mask Res Mask VCC2/3 Value* Aux1 Value Reserved Host PW Bit6* bit13 bit12 EE L-LO-TEMPAL L-LO-RX-PAL L-LO-TEMPW VCC5/3/2 Vee Apd/Tec/ Wave/Res Flags Alarm Flags Apd/Tec/Wave/ Res Mask VCC5/3/2/Vee Alarm Mask Bias Value Aux2 Value TX-P Value GCS1 GCS0 Host PW Table Select Bit0** bit1 bit0 Lock-T1-221 L-LO-TXP-AL Reserved Reserved Host PW Bit7 bit15 bit14 EE L-HI-TEMPAL L-HI-RX-P-AL L-HI-TEMP-W Reserved POA PWE (MSB) EXPANDED BYTES Bit5 Bit4 Bit3 bit7 EE Reserved PEC_EN PWE (LSB) Bit2 bit5 bit4 EN2 Value Bit1 bit3 bit2 EN1 Value bit11 bit10 bit9 EE bit8 bit6 EE Reserved L-HI-AUX1AL Reserved Reserved L-LO-AUX1AL Reserved L-LO-BIASL-HI-BIAS-AL L-HI-TX-P-AL AL L-HI-AUX2AL L-LO-AUX2AL Reserved <1> <1> L-HI-BIAS-W L-LO-BIAS-W L-HI-TX-P-W L-LO-TX-P-W Reserved Reserved L-RESETDONE Reserved <1> L-HI-RX-P-W L-LO-RX-P-W L-HI-AUX1-W L-TX-NR L-APD-SUP-F L-TX-F L-TEC-F L-TX-CDR-NL L-WAVE-NL L-LO-AUX1L-LO-AUX2L-HI-AUX2-W W W L-RX-NR Reserved L-RX-LOS Reserved <1> <1> <1> L-RX-CDR-NL L-MOD-NR Reserved Reserved L-LO-VCC5L-LO-VCC3L-LO-VCC2L-LO-VEE5L-HI-VCC5-AL L-HI-VCC3-AL L-HI-VCC2-AL L-HI-VEE5-AL AL AL AL AL *VCC2/3 are in reserved locations. 26 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DS1862 EXPANDED BYTES (CONTINUED) BYTE (hex) 57 58 59 5A 5B 5C 5D 5E 5F 6E 6F 74 77 78 79 7A 7B 7C 7D 7E 7F BYTE/WORD NAME <1> <1> Bit7 bit15 bit14 Bit6* bit13 bit12 Bit5 bit11 bit10 Bit4 bit9 bit8 Bit3 bit7 bit6 Bit2 bit5 bit4 Bit1 bit3 bit2 Bit0** bit1 bit0 L-HI-VCC5-W L-LO-VCC5-W L-HI-VCC3-W L-LO-VCC3-W L-HI-VCC2-W L-LO-VCC2-W L-HI-VEE5-W L-LO-VEE5-W HI-TEMP-AL LO-TEMP-AL MASK MASK HI-RX-P-AL MASK HI-TEMP-W MASK HI-RX-P-W MASK Reserved Reserved HI-BIAS-AL MASK LO-BIAS-AL MASK HI-TX-P-AL MASK Reserved HI-TX-P-W MASK Reserved MOD-NR MASK Reserved HI-VEE5-AL MASK HI-VEE5-W MASK RX-LOS Reserved Reserved 225 217 29 21 225 217 29 21 21 LO-TX-P-AL MASK Reserved LO-TX-P-W MASK Reserved RESETDONE MASK Reserved LO-VEE5-AL MASK LO-VEE5-W MASK DATA-NR Reserved Reserved 224 216 28 20 224 216 28 20 20 <1> LO-RX-P-AL HI-AUX1-AL LO-AUX1-AL HI-AUX2-AL LO-AUX2-AL MASK MASK MASK MASK MASK LO-TEMP-W MASK LO-RX-P-W MASK Reserved HI-AUX1-W MASK Reserved LO-AUX1-W MASK HI-BIAS-W MASK HI-AUX2-W MASK RX-LOL MASK Reserved LO-BIAS-W MASK LO-AUX2-W MASK RX-CDR-NL MASK Reserved <1> <1> <1> TX-NR MASK TX-F MASK APD-SUP-F TEC-F MASK MASK TX-CDR-NL RX-NR MASK MASK WAVE-NL MASK Reserved <1> <1> HI-VCC5-AL LO-VCC5-AL HI-VCC3-AL LO-VCC3-AL HI-VCC2-AL LO-VCC2-AL MASK MASK MASK MASK MASK MASK HI-VCC5-W MASK TX-D TX-NR POA 231 223 215 27 231 223 215 27 27 LO-VCC5-W MASK SOFT TX-D TX-F Reserved 230 222 214 26 230 222 214 26 26 HI-VCC3-W MASK MOD-NR TX-CDR-NL Reserved 229 221 213 25 229 221 213 25 25 LO-VCC3-W MASK P-DOWN/RST RX-NR Reserved 228 220 212 24 228 220 212 24 24 HI-VCC2-W MASK SOFT P-DOWN RX-CDR-NL Reserved 227 219 211 23 227 219 211 23 23 LO-VCC2-W MASK INTERRUPT Reserved Reserved 226 218 210 22 226 218 210 22 22 <1> <1> <1> POA <1> Host PW<6> Host PW<6> Host PW<6> Host PW<6> PWE<6> PWE<6> PWE<6> PWE<6> Table Select<1> *Bit 6 and Bit 3 of Byte 6Eh are masked by Bit 6 and Bit 5 of Byte DDh in Table 01h, respectively. **Bit 0 of Address 01h can be written only if Bit 0 of Byte DDh in Table 01h is set. ____________________________________________________________________ 27 XFP Laser Control and Digital Diagnostic IC DS1862 TABLE 01H (SERIAL ID MEMORY) ADDRESS (hex) 80<2> 88<2> 90<2> 98<2> A0<2> A8<2> B0<2> B8<2> C0<2> C8<2> D0<2> D8<2> E0<2> E8<2> F0<2> F8<2> BYTE (hex) DC<2> DD<2> LO Mem EN WORD 0 Byte 0/8 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE BYTE/WORD NAME EE Bit7 bit15 bit14 EE Reserved Reserved Byte 1/9 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE Bit6 bit13 bit12 EE Reserved Enable 6Eh, bit 6 EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE Bit5 bit11 bit10 EE Reserved Enable 6Eh, bit 3 WORD 1 Byte 2/A Byte 3/B EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EXPANDED BYTES Bit4 bit9 EE Reserved Reserved bit8 Bit3 bit7 EE Reserved Reserved bit6 Bit2 bit5 EE Reserved Reserved bit4 Bit1 bit3 EE Reserved Reserved bit2 Bit0 bit1 EE VCC2/3_Sel LOCK-bit bit0 EE EE EE EE EE EE EE EE EE EE EE VCC2/3_Sel EE EE EE EE WORD 2 Byte 4/C Byte 5/D EE EE EE EE EE EE EE EE EE EE EE LO Mem 6Eh enable EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE AUX1/2 Unit Select EE EE EE EE WORD 3 Byte 6/E Byte 7/F EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE DE<2> AUX1/2 UNIT SEL AUX1-SEL 23 AUX1-SEL 22 AUX1-SEL 21 AUX1-SEL 20 AUX2-SEL 23 AUX2-SEL 22 AUX2-SEL 21 AUX2-SEL 20 Note: Byte DDh <6:5> of Table 01h enables bit 6 and bit 3 of Byte 6Eh in the lower memory. TABLE 02H (HOST USER MEMORY) ADDRESS (hex) 80-FF<3> WORD 0 Byte 0/8 EE Byte 1/9 EE EE WORD 1 Byte 2/A Byte 3/B EE EE WORD 2 Byte 4/C Byte 5/D EE EE WORD 3 Byte 6/E Byte 7/F EE TABLE 03H (MODSET LOOK-UP TABLE) ADDRESS (hex) 80-87<4> 88-BF<4> C0-C7<4> WORD 0 Byte 0/8 EE, < -40C -- EE, +88C Byte 1/9 EE, -40C -- EE, +90C EE, -38C -- EE, +92C WORD 1 Byte 2/A Byte 3/B EE, -36C -- EE, +94C EE, -34C -- EE, +96C WORD 2 Byte 4/C Byte 5/D EE, -32C -- EE, +98C EE, -30C -- EE, +100C WORD 3 Byte 6/E Byte 7/F EE, -28C -- EE, > +102C 28 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DS1862 TABLE 04H (CONTROL AND CONFIG) (80H-BBH) ADDRESS (hex) 80<4> 88<4> 90<4> 98<4> A0<4> A8<4> B0<4> B8<4> WORD 0 Byte 0/8 Reserved Quick trip TX-P high Reserved Scale MSB RX-P Offset MSB temp Offset MSB RX-P LUT INDEX pointer Module PWD setting Byte 1/9 Bias shift, TX-P shift Quick trip TX-P low Reserved Scale LSB RX-P Offset LSB temp Offset LSB RX-P LUT value Module PWD setting Byte 2/A RX-P shift AUX1 shift QT high bias setting Scale MSB VCC3 Scale MSB AUX1 Offset MSB VCC3 Offset MSB AUX1 LUT_conf Module PWD setting WORD 1 Byte 3/B AUX2 shift Reserved Control Register 2 Scale LSB VCC3 Scale LSB AUX1 Offset LSB VCC3 Offset LSB AUX1 Reserved Module PWD setting EXPANDED BYTES BYTE (hex) 81 82 83 84 85 86 87 8B B2 B4 B8 B9 BA BB BYTE Bit7 WORD NAME bit15 bit14 <4> <4> WORD 2 Byte 4/C APC course setting Reserved Scale MSB BIAS Scale MSB AUX2 Offset MSB Bias Offset MSB AUX2 DAC status Byte 5/D APC fine setting Reserved Scale LSB BIAS Scale LSB AUX2 Offset LSB BIAS Offset LSB AUX2 Reserved WORD 3 Byte 6/E LUT current range Reserved Scale MSB TX-P Reserved Offset MSB TX-P Reserved Reserved Byte 7/F Control Register 1 Reserved Scale LSB TX-P Reserved Offset LSB TX-P Reserved Reserved Bit6 bit13 bit12 Bit5 bit11 bit10 bit9 Bit4 bit8 bit7 Bit3 bit6 Bit2 bit5 bit4 bit3 Bit1 bit2 Bit0 bit1 bit0 Bias shift 23 Bias shift 22 RX-P shift 23 AUX2 shift 23 APC 29 Reserved Reserved FET_POL Reserved Reserved Safety flag 231 223 215 27 Rx-P shift 22 AUX2 shift 22 APC 28 Reserved Reserved QT TX-P HI mask Reserved Reserved Shutdown 230 222 214 26 Bias shift 21 Rx-P shift 21 AUX2 shift 21 APC 27 Reserved Reserved QT BIAS HI mask Reservedenable Reserved Reserved 229 221 213 25 Bias shift 20 Rx-P shift 20 AUX2 shift 20 APC 26 Reserved Reserved QT TX-P LO mask TEMP_int-ext Reserved QT TX-P LO FLAG 228 220 212 24 TX-P shift 23 AUX1 shift 23 Reserved APC 25 Reserved Reserved Reserved Reserved Reserved QT TX-P HI FLAG 227 219 211 23 TX-P shift 22 AUX1 shift 22 Reserved APC 24 Reserved TX-P shift 21 AUX1 shift 21 Reserved APC 23 APC 21 TX-P shift 20 AUX1 shift 20 Reserved APC 22 APC 20 <4> <4> <4> <4> <4> LUT range 22 LUT range 21 LUT range 20 Reserved EN Value 21 SEEB QT BIAS HI FLAG 226 218 210 22 scr_sink_b EN Value 20 TEN Reserved 225 217 29 21 Reserved EN1/2 MUX AEN Reserved 224 216 28 20 <4> LUT_C ONF <4> <4> Module PW<7> Module PW<7> Module PW<7> Module PW<7> ____________________________________________________________________ 29 XFP Laser Control and Digital Diagnostic IC DS1862 TABLE 05H (OPTIONAL OFFSETS AND THRSET) ADDRESS (hex) 80-87 BYTE (hex) 80 82 87 WORD 0 Byte 0/8 Byte 1/9 DS60 SCALE BYTE/WORD NAME DS60 SCALE <5> LM50 SCALE <5> VTHRSET_Value Bit7 bit15 215 215 27 214 214 WORD 1 Byte 2/A Byte 3/B LM50 SCALE Bit6 213 213 26 212 212 Bit5 bit11 bit10 211 211 25 210 210 29 29 24 WORD 2 Byte 4/C Reserved Bit4 bit9 bit8 28 28 Byte 5/D Reserved Bit3 bit7 27 27 23 bit6 26 26 Byte 6/E Reserved Bit2 bit5 25 25 22 bit4 24 24 23 23 21 WORD 3 Byte 7/F VTH DAC Value <1> Bit1 bit3 bit2 22 22 Bit0 bit1 21 21 20 bit0 20 20 EXPANDED BYTES bit14 bit13 bit12 Detailed Register Description Conventions Name of Row * Name of Byte ................... Lower Memory 00h * User EE ............................< R-all / W-all > 30 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DS1862 Bit 0: DATA_NOT_READY. Bit is high until DS1862 has achieved power-up. Bit goes low, signaling that monitor channel data is ready to be read. Bit 1: RX-LOS. Indicates optical loss of the signal and is updated within tLOS-ON. Bit 2: Interrupt. Indicates the state of the INTERRUPT pin and is updated within tINIT ON. Bit 3: Soft P-DOWN/RST. R/W bit that places the DS1862 in power-down mode. Toggle to reset. Bit 4: P-DOWN/RST. Indicates the digital state of the P-DOWN/RST pin and is updated within tPDR-ON. Bit 5: MOD_NR State. Indicates the state of MOD_NR pin and is updated within tPDR-ON. Bit 6: Soft TX-D. R/W bit that disables (shuts down) IBIASSET and IMODSET. Bit 7: TX-D. Indicates the digital state of the TX-D pin and is updated within tOFF. 6Fh * 6Fh GCS0 ........................< R-all / W-all > Table 01h 80h DBh * User EE ............................< R-all / W-Module > ____________________________________________________________________ 31 XFP Laser Control and Digital Diagnostic IC DDh * 6Eh Enable ......................< R-all / W-Module > DS1862 Table 02h 80h FFh * User EE ............................< R-all / W-Host > Table 03h 80h C7h * LUT ..................................< R-Module / W-Module > Table 04h 80h B8h 81h * Bias shift ..........................< R-Module / W-Module > 32 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC 85h * APC REF FINE .................< R-Module / W-Module > DS1862 ____________________________________________________________________ 33 XFP Laser Control and Digital Diagnostic IC 92h VCC2/3 SCALE ...........................< R-Module / W-Module > DS1862 This 16-bit This 16-bit This 16-bit This 16-bit * AUX1 SCALE ...................< R-Module / W-Module > This 16-bit register con- This 16-bit register con- This 16-bit register con- This 16-bit register con- B0h * LUT INDEX PNTR.............< R-Module / W-Module > 34 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC B1h * LUT VALUE ......................< R-Module / W-Module > DS1862 Table 5 B8h * MOD_PW_CHNG .............< R-Module / W-Module > ____________________________________________________________________ 35 XFP Laser Control and Digital Diagnostic IC DS1862 Security/Password Protection The DS1862 features two separate and independent 32-bit passwords for important memory locations. The host password and the module password allow their own allocated memory locations to be locked to prevent write and/or read access. To enhance the security of the DS1862, the Password Entry and Setting bytes can never be read. To gain access to host-protected or module-protected memory locations, the correct 32-bit value must be entered in to the password entry bytes (PWE) in either a single four-byte write, or four single-byte writes. To reprogram either password, simply enter the appropriate current password to gain memory access, write the new Host or Module PW with one four-byte write, and finally reenter the new password into the PWE to regain memory access. Precision SCALE Register Settings for AUX2MON The DS1862 features a factory-trimmed SCALE value for use with DS60 or LM50 temperature sensors. If external temperature measurement on AUX2MON is used with one of these two sensors, the 16-bit SCALE value can be read from Table 05h and written into the SCALE register in Table 04h, Byte 9Ch and 9Dh. This option allows for the most precise setting for SCALE without requiring additional trimming. Since the SCALE register value is precisely trimmed at the factory, the OFFSET register will always be a non-unique value and can simply be written into are OFFSET register. For the DS60, the value of EF0Ah in OFFSET completes the internal calibration. For the LM50, the value of F380h in OFFSET completes the internal calibration. Power-Up Sequence The DS1862 does require a particular power-up sequence to ensure proper functionality. VCC3 should always be applied first or at the same time as VCC2. If this power-up sequence is not followed, then current can be sourced out of VCC2 as if it was connected to VCC3 with a resistor internal to the DS1862. If VCC2 is not used then it should be externally connected to VCC3. I2C Serial Interface I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions. Slave devices: Slave devices send and receive data at the master's request. Bus idle or not busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. Start condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See Figure 14 for applicable timing. Stop condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See Figure 14 for applicable timing. Repeated start condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See Figure 14 for applicable timing. Signal Conditioners-- EN1 and EN2 and VTHRES Signal Conditioners--EN1 and EN2 The EN1 and EN2 output pins are controlled by the bits at address 01h, bits 2 and 1. The logic state of the pins is directly analogous to the logical state of the register. EN1 and EN2 automatically change to a high and low state, respectively, during power-down mode as described in the Power-Down Functionality section. Signal Conditioners--VTHRES A programmable voltage source, THRSET is also provided for use with signal conditioners. This source is programmable from 0 to 1V in 256 increments. I2C and Packet Error Checking (PEC) Information The DS1862 supports I2C data transfers as well as data transfers with PEC. The slave address is unalterable and is set to A0h. The DS1862, however, does have an additional dedicated pin, MOD-DESEL, which acts as an active-low chip select to enable communication. See the I2C Serial Interface and the I2C Operation Using Packet Error Checking sections for details. 36 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (Figure 14). Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 14) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 14) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave address byte: Each slave on the I 2 C bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1862's slave address is 1010000Xb. The MODDESEL pin is used as a chip select, and allows the device to respond or ignore I2C communication that has A0h as the device address. By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master will read data from the slave. If an incorrect slave address is written, the DS1862 assumes the master is communicating with another I2C device and ignores the communications until the next start condition is sent. Memory address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. DS1862 SDA tBUF tLOW tR tF tHD:STA tSP SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO Figure 14. I2C Timing Diagram ____________________________________________________________________ 37 XFP Laser Control and Digital Diagnostic IC DS1862 The memory address is always the second byte transmitted during a write operation following the slave address byte. Writes that do not modify all 4 bytes on the row are allowed and do not corrupt the remaining bytes of memory on the same row. Because the whole row is written, bytes on the row that were not modified during the transaction are still subject to a write cycle. This can result in a whole row being worn out over time by writing a single byte repeatedly. Writing a row one byte at a time wears out the EEPROM four times faster than writing the entire row at once. The DS1862's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. Reading a single byte from a slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave at the location currently in the address counter; the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 15 for a read example using the repeated start condition to specify the starting memory location. Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter's location before the read cycle. If the address counter reaches the last physical address, the internal index pointer loops back to the first memory location in a given memory table. For example, if address FFh in Table 02h is read, the next byte of data to be returned to the master is address 80h in Table 2, not 00h in lower memory. I2C Communication Writing a single byte to a slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations. Writing multiple bytes to a slave: To write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 4 data bytes, and generates a stop condition. The DS1862 is capable of writing 1 to 4 bytes (referred to as 1 row or page) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one row of the memory map. Attempts to write to additional memory rows without sending a stop condition between rows results in the address counter wrapping around to the beginning address of the present row. To prevent address wrapping from occurring, the master must send a stop condition at the end of the row, and then wait for the bus free or EEPROM write time to elapse. Then the master can generate a new start condition, write the slave address byte (R/W = 0), and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time EEPROM is written, the DS1862 requires the EEPROM write time (tW) after the stop condition to write the contents of the row to EEPROM. During the EEPROM write time, the DS1862 does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS1862, which allows the next row to be written as soon as the DS1862 is ready to receive the data. The alternative to acknowledge polling is to wait for the maximum period of tW to elapse before attempting to write again to the DS1862. EEPROM write cycles: When EEPROM writes occur, the DS1862 writes the whole EEPROM memory 4-byte row even if only a single byte on the row was modified. 38 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC DS1862 COMMUNICATIONS KEY S START A ACK NOT ACK X X X X X WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA X X X 8-BITS ADDRESS OR DATA NOTE: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. P STOP REPEATED START N SR WRITE A SINGLE BYTE S 10 1 00 0 0 0 A MEMORY ADDRESS A DATA A P WRITE UP TO A 4-BYTE PAGE WITH A SINGLE TRANSACTION S 10 1 00 0 0 0 A MEMORY ADDRESS A DATA A DATA A P READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER S 10 1 00 0 0 0 A MEMORY ADDRESS A SR 10 1 00 0 0 0 A DATA N P READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER S 10 1 00 0 0 0 A MEMORY ADDRESS A SR 10 1 00 0 0 0 A DATA A DATA A DATA A DATA N P Figure 15. I2C Communications Examples I2C Operation using Packet Error Checking Read Operation with Packet Error Checking Packet error checking during reads is supported by the DS1862. Information is transferred form the DS1862 in much the same way as conventional I2C protocol, however, an extra CRC field is added and checked. The still begins by sending the device address (A0h for DS1862), then the index pointer to the memory address of interest. The next byte transferred, however will be the value of the intended number of bytes to be read. The calculation of the CRC-8 includes and requires the explicit starting memory address to be included as the second transferred byte (dummy write byte). Next, the slave transfers the data back as the master acknowledges. Only 1 to 128 bytes can be sequentially read during one transmission while using PEC. After the master reads the intended number of bytes, the CRC-8 value is transmitted by the DS1862. The master ends the communication with a NACK and a STOP. See Figure 16 for a graphical representation. The CRC-8 is calculated starting with the MSB of the memory address pointer, number of bytes to read, and the read data. The master can then verify the CRC-8 value and reject the read data if the CRC-8 value does not correspond to the received CRC value. The CRC-8 must be calculated by using the following polynomial for both reads and writes: C(x) = X8 +X2 + X + 1 Write Operation with Packet Error Checking Packet error checking during writes is also supported by the DS1862. Information is written to the DS1862 in much the same way as conventional I2C protocol, however, an extra CRC field is added and checked. The master still begins by sending the device address, then the index pointer to the memory address of interest. The next byte however, will be the value of the intended number of bytes to be written. The calculation of the 39 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC CRC-8 includes and requires the explicit starting memory address to be included as the second transferred byte. Next, the master transfers the data as the DS1862 acknowledges. Only 4 bytes can be sequentially written during one transmission while using PEC. After the master writes the intended number of bytes, the CRC-8 value should be transmitted. Following the CRC-8 byte the master should transmit the CAB byte (CRC Add-on Byte). At this point, the DS1862 sends an ACK if the CRC-8 matches its internal calculated value or a NACK if not. Finally the master should end the communication and send a STOP. See Figure 16 for a graphical representation. The CRC-8 is calculated starting with the MSB of the memory address pointer, number of bytes to be written, and the written data. The master can then poll the last ACK or NACK for successful transfer of written data. For more information on I 2 C PEC communications, please refer to the XFP and/or SMBus 2.0 standard. DS1862 Applications Information Calibrating APC and Extinction Ratio Before calibrating, the APC register should be set to a low value to ensure the laser's maximum power level is not exceeded before the power level is calibrated. Additionally, the ER should be set to a minimum value to ensure that a data test pattern does not cause the laser to shut off. Once the APC and ER registers are at minimal values, enable a data pattern and calibrate the average power level. Calibrating the Average Power Level While sending data through the laser diode, increase the value in the APC register until the light output matches the desired average power level. The average power level is the arithmetic average of the `1' and `0' power levels. COMMUNICATIONS KEY S START A ACK NOT ACK X X X X X WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA X X X 8-BIT ADDRESS OR DATA NOTE: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. P STOP REPEATED START N SR WRITE UP TO A 4-BYTE PAGE WITH A SINGLE TRANSACTION USING PEC S 10 1 00 0 0 0 A MEMORY ADDRESS A NUMBER OF BYTES A DATA A DATA A DATA A DATA A CRC-8 VALUE A DATA A (IF CRC-8 IS CORRECT) P READ 1-128 BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER S 10 1 00 0 0 0 A MEMORY ADDRESS A NUMBER OF BYTES A SR 10 1 00 0 0 0 A DATA A DATA A CRC-8 VALUE N P Figure 16. I2C PEC Communications Examples 40 ____________________________________________________________________ XFP Laser Control and Digital Diagnostic IC Power-Supply Decoupling To achieve best results, it is recommended that the power supply is decoupled with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC2/VCC3 and GND pins to minimize lead inductance. SDA and SCL Pullup Resistors SDA is an open-collector bidirectional data pin on the DS1862 that requires a pullup resistor to realize high logic levels. Either an open-collector output with a pullup resistor or a push-pull output driver can be utilized for the SCL input. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC Electrical Characteristics are within specification. DS1862 Typical Operating Circuit 1.8V 3.3V 0.1F 0.1F HOST 3.3V 3.3V 1k 4.7k 4.7k VCC2 SDA OUT SCL TX-DISABLE 3.3V 3.3V 3.3V MOD-DESEL 10k 10k 10k P-DOWN/RST RX-LOS MOD-NR INTERRUPT AUX1MON * AUX2MON SC-TX-LOS GND BMD RSSI THRSET SC-RX-LOS SC-RX-LOL EN2 EN1 VTH LOS LOL FCTL2 FCTL1 FCTL1 FCTL2 LOS TX-D BIASMON BIASSET TX-DISABLE MON BIASSET DISABLE MODSET VCC3 FETG 10nF MAX3975 LASER DRIVER DS1862 MODSET MAX3991 LIMITING AMP MAX3992 EQUALIZER RECEIVER CURRENT SENSE (VOLTAGE) 1nF *ADDITIONAL MONITORS NOT USED IN THIS EXAMPLE. ____________________________________________________________________ 41 XFP Laser Control and Digital Diagnostic IC DS1862 Chip Topology TRANSISTOR COUNT: 75,457 SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 42 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Heaney |
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